High-speed computation is a critical design factor in many systems such as computers, signal processors, and process controllers. The systems increasingly rely on a limited number of LSI integrated circuits to perform floating point calculations.
A number of multi-chip implementations of floating point processes have become available on the market. These implementations can be roughly divided into two classes: those based on a microprocessor and those based on a bit slice family. The microprocessor based co-processors are often single chip solutions, but are slower than the bit slice family because of the higher degree of parallelism in the math execution in the bit slice approaches. Most bit slice approaches use separate chips for multiplication operations and addition operations.
Recently, a processor having combined multiplication and addition operations on one integrated circuit has become available. However, the multiplication and addition functions cannot be performed in parallel. As a result, common operations such as sum of products and product of sums require additional clock cycles.
Thus, a need has arisen in the industry for a floating point architecture, which allows simultaneous operation of multiplying and adding functions and enabling fast computation of sums of products and product of sums.